1. Field of the Invention
The present invention relates to an isolation method for a semiconductor device, and more particularly, to a trench isolation method for a semiconductor device.
2. Description of the Related Art
An isolation method in manufacturing of a semiconductor device is generally either a local oxidation of silicon (LOCOS) method or a trench isolation method.
In particular, the LOCOS method is simple, and has the advantage that a wide area and a narrow area can simultaneously be isolated. However, in a LOCOS method, a bird's beak caused by lateral oxidation can widen an isolation area, thereby reducing the effective area of a source/drain region. Also, when forming a field oxide layer, stress due to a difference in thermal expansion coefficients is concentrated on the edge of the oxide layer. As a result, crystalline defects can occur in a silicon substrate, causing high leakage currents.
As a result of this, a trench isolation method capable of implementing a smaller isolation area than by the LOCOS method is required. In this method, a trench formed in a silicon substrate is filled with dielectric material such as an oxide, to increase the effective isolation length.
However, one of the big problems in implementing a trench isolation structure is that a strong electric field is locally formed in a channel area adjacent to the side wall of the trench, so inversion easily occurs even at a low voltage, thereby increasing the current flowing between the source and the drain. In particular, when using a shallow trench isolation (STI) structure in a highly integrated semiconductor device, electrical characteristics of the device are determined by the profile of the edge of the trench.
FIG. 1 is a section view illustrating problems of a conventional shallow trench isolation (STI) method.
In FIG. 1, reference numeral 100 represents an active region, and reference numeral 200 represents an oxide layer filled in an STI region, which acts as a field region. Also, reference character "A" represents a profile before the oxide layer is wet-etched, and dashed lines designated by reference character "B" represent a profile after the wet-etching.
The oxide layer 200 filled in the trench is deposited by a general chemical vapor deposition (CVD) method. The oxide layer formed by the CVD method has a higher etching rate during the wet-etching process than a thermal oxide layer. As a result, the oxide layer 200 filled in the trench is etched excessively during the processes for etching various oxide layers such as pad oxide layer, sacrificial oxide layer and the oxide layer used as a buffer layer for ion implantation, which essentially follow the trench filling step. Because of this, the final height of the oxide layer 200 remaining in the trench is less than that of the active region 100, so the active region adjacent to the trench is exposed (as designated by reference character "C"). As a result, a hump phenomenon, where a transistor is turned on twice, and an inverse narrow width effect are caused as shown in FIG. 2, thereby deteriorating the performance of the transistor.
FIG. 2 is a graph showing characteristics of drain current of a transistor according to gate voltage. In the graph of FIG. 2, V.sub.B is 3V, and the transistor is turned on twice.
FIG. 3 is a graph showing an inverse narrow width effect by the conventional STI method. Here, as shown in FIG. 3 the inverse narrow width effect means that a threshold voltage decreases as the channel length of a transistor decreases. Reference character X represents the result observed before the hump phenomenon occurs, and reference character Y represents the result observed after the hump phenomenon occurs.
Recently, a method of thermally oxidizing polysilicon deposited in a trench after forming the trench has been suggested. According to this method, if the trench width is narrow, the trench may be completely filled by volumetric expansion while the polysilicon is oxidized. However, there is a problem in that stress is applied to the active region at the side wall of the trench. Also, due to the step coverage limitation of the polysilicon deposited in the trench, a collapse at the upper edge of the trench cannot effectively be prevented.